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mc145421 ? mc145425 motorola 1
(udlt ii) the mc145421 and mc145425 udl t s are highspeed data transceivers capable of providing 160 kbps fullduplex data communication over 26 a wg and larger twistedpair cable up to 1 km in length. these devices are primarily used in digital subscriber voice and data telephone systems. in addition, the devices meet and exceed the ccitt recommendations for data transfer rates of isdns on a single twisted pair . the devices utilize a 512 kbaud mdpsk burst modulation technique to supply the 160 kbps fullduplex data transfer rates. the 160 kbps rate is provided through four channels. there are two b channels, which a r e 6 4 k bp s e ach . i n a ddition , t her e a r e t w o d c hannel s w hic h a re 16 kbps each. the mc145421 and mc145425 udl t s are designed for upward compatibility with the existing mc145422 and mc145426 80 kbps udl t s, as well as compa tibility with existing and evolving telephone switching hardware and software architectures. the mc145421 (master) udl t is designed for use at the telephone switch line card while the mc145425 (slave) udl t is designed for use at the remote digital telset or data terminal. ? employs cmos technology in order to take advantage of its proven capability for complex analog and digital lsi functions ? provides synchronous fullduplex 160 kbps voice and data communication in a 2b+2d format for isdn compatibility ? provides the ccitt basic access data transfer rate (2b+d) for isdns on a single twisted pair up to 1 km ? compatible with existing and evolving telephone switch architectures and call signaling schemes ? protocol independent ? single + 5 v power supply ? mc145421evk is available 16 kbps d2 64 kbps b1 64 kbps b2 16 kbps d1 16 kbps d2 64 kbps b1 64 kbps b2 twisted pair wire 1 km master isdn udlt 160 kbps fullduplex data transmission slave isdn udlt 16 kbps d1 order this document by mc145421/d
semiconductor technical data p suffix plastic package case 709 dw suffix sog package case 751f ordering information mc145421p plastic package mc145425p plastic package MC145421DW sog package mc145425dw sog package 24 1 24 1 ? motorola, inc. 1995 rev 2 (replaces adi1251) 9/95 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc145421 ? mc145425 motorola 2 pin assignments d1i lb li v ref v ss dclk d2i vd re2 rx lo2 lo1 v dd te1 msi cci 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 13 11 12 21 22 23 24 tx te2 tdc/rdc re1 se pd d2o d1o mc145421 e master (plastic and sog packages) d1i lb li v ref v ss dclk d2i vd bclk rx lo2 lo1 v dd en1 tone cci 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 13 11 12 21 22 23 24 tx en2 xtl clkout mu/a pd d2o d1o mc145425 e slave (plastic and sog packages) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc145421 ? mc145425 motorola 3 23 22 4 11 16 17 12 5 3 2 modulator b1 b1 b1 b1 b2 b2 b2 b2 d1 d1 d1 d1 d2 d2 d2 lo1 lo2 lb se msi cci pd vd li v ref demodulator sequence and control 8 8 2 2 8 8 2 2 b channel buffers b channel buffers d channel buffers 7 6 20 21 19 10 8 18 13 15 14 d2i d1i re2 rx re1 d2o d1o tdc/rdc tx te1 te2 d channel buffers + dclk 9 d2 mc145421 master isdn block diagram b1 b1 b1 b1 b2 b2 b2 b2 d1 d1 d1 d1 d2 d2 d2 d2 lo1 lo2 cci lb pd vd li v ref xtl mu/a tone 23 22 17 18 4 11 16 19 5 3 2 modulator osc demodulator sequence and control 8 8 2 2 2 2 2 8 8 b channel buffers b channel buffers d channel buffers d channel buffers 7 6 10 8 9 20 13 15 14 21 d2i d1i rx d2o dclk d1o tx bclk en1 en2 + 12 clkout mc145425 slave isdn block diagram f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc145421 ? mc145425 motorola 4 absolute maximum ratings (voltage referenced to v ss ) rating symbol value unit dc supply voltage v dd v ss 0.5 to 6.5 v voltage any pin to v ss v 0.5 to v dd + 0.5 v dc current, any pin (excluding v dd , v ss ) i 10 ma operating temperature t a 40 to + 85 c storage temperature t stg 85 to + 150 c recommended operating conditions (t a = 40 to + 85 c ) parameter pins min typ max unit dc supply voltage v dd 4.5 5.0 5.5 v frame rate mc145421 (see note) msi e 8.0 e khz mc145421/25 frame slip rate (see note) e e e 0.25 % cci clock frequency e e 8.192 8.29 mhz tdc/rdc data clocks (for master) e 0.128 e 4.1 mhz dclk e 0.016 e 4.1 mhz modulation baud rate (cci/16) lo1, lo2 e 512 e khz note: the slave' s crystal frequency divided by 1024 must equal the master ' s msi frequency 0.25% for optimum operation. also, the 8.192 mhz input at the master divided by 1024 must be within 0.048% of the master 's 8 khz msi clock frequency. digital characteristics (v dd = 5 v, t a = 40 to + 85 c) parameter min max unit input high level 3.5 e v input low level e 1.5 v input current, v dd e 15 ma input current (digital pins) e 5 m a input capacitance e 10 pf output high current (except tx on master and slave, and pd on the slave) v oh = 2.5 v oh = 4.6 1.7 0.36 e e ma tx output high current v oh = 2.5 v oh = 4.6 3.4 0.7 e e ma pd (slave) output high current (see note) v oh = 2.5 e 90 m a output low current (except tx on master and slave, and pd on slave) v ol = 0.4 v ol = 0.8 0.36 0.8 e e ma tx output low current v ol = 0.4 v ol = 0.8 1.7 3.5 e e ma pd (slave) output low current (see note) v ol = 0.4 30 60 m a tx threestate impedance 100 e k w xtl output high current v oh = 4.6 e 450 m a xtl output low current v oh = 0.4 450 e m a note: to overdrive pd from a low level to 3.5 v , or a high level to 1.5 v requires a minimum of 800 m a drive capability. analog characteristics (v dd = 5 v, t a = 0 to 70 c) parameter min max unit modulation differential amplitude rl = 880 w (lo1 lo2) 4.6 e vpeak modulation differential dc offset e 40 mv v ref voltage (typically 9/20 (v dd v ss )) 2.0 2.5 v pcm tone level 22 18 dbm demodulator input amplitude 50 e mvpeak demodulator input impedance (li to v ref ) 75 300 k w this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however , it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high imped - ance circuit. for proper operation it is recom - mended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss or v dd ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc145421 ? mc145425 motorola 5 mc145421 master pin descriptions v dd positive supply (pin 24) the most positive power supply pin, normally + 5 v with respect to v ss . v ss negative supply (pin 1) the most negative supply pin and logic ground, normally 0 v. v ref reference output (analog ground) (pin 2) this pin is the output of the internal reference supply and should be bypassed to v dd and v ss with 0.1 m f capacitors. this pin usually serves as an analog ground reference for transformer coupling of the device' s incoming bursts from the line. no external dc load should be placed on this pin. li line input (pin 3) this pin is an input to the demodulator for the incoming bursts. the input has an internal 240 k w resistor tied to the v ref pin, so an external capacitor or line transformer may be used to couple the input signal to the device with no dc of fset. lo1, lo2 line driver outputs (pins 23, 22) these pushpull outputs drive the twisted pair transmis - sion line with a 512 khz modified dpsk (mdpsk) burst each 125 m s, in other words at an 8 khz rate. when not modulating the l ine , t hes e p in s a re d rive n t o t h e a ctiv e h ig h s tat e e being t h e s am e p otential , t he y c reat e a n a c s hort . w hen used in conjunction with feed resistors, proper line termina- tion is maintained. se signal enable input (pin 11) at the time of a negative transition on this pin, an internal latch stores the states of lb and pd for as long as se is held low. during this time, the vd, do1, and do2 outputs are driven to the highimpedance state. when se is high, all pins function normally. lb loopback control (pin 4) a low level on this pin ties the internal modulator output to the internal demodulator input, which loops the entire burst for testing purposes. during the loopback operation, the li input is ignored and the lo1 and lo2 drivers are driven to the active high level. the state of this pin is internally latched if the se pin is held low . this feature is only active when the pd input is high. pd powerdown input (pin 12) when held low the isdn udl t powers down, except the circuitry that is necessary to demodulate an incoming burst and to output vd, b, and d channel data bits. when pd is brought h igh , t h e i sd n u dl t p ower s u p. t hen , i t b egins transmittin g e ver y m si p eriod t o t h e s lav e d evice , s hortly after the rising edge of msi. the state of this pin is latched if the se pin is held low. vd valid data output (pin 5) a high level on this pin indicates that a valid line transmis- sion has been demodulated. a valid transmission burst is determined by proper synchronization and the absence of detected bit errors. vd changes state on the rising edge of msi when pd is high. when pd is low , vd changes state at the end of demodulation of a transmission burst and does not change again until three msi rising edges have occurred, at which time it goes low , or until the next demodulation of a burst. vd is a standard bseries cmos output and is high impedance when se is low. msi master sync input (pin 16) this pin is the master , 8 khz frame reference input. the rising edge of msi loads b and d channel data which had been input during the previous frame into the modulator sec - tion of the device and initiates the outbound burst onto the twistedpair cable. the rising edge of msi also initiates the buffering of the b and d channel data demodulated during the p reviou s f rame . m s i s houl d b e a pproximately l eading edge aligned with the tdc/rdc data clock input pin. cci highspeed clock input (pin 17) an 8.192 mhz clock should be supplied to this input. the 8.192 mhz input should be 50% duty cycle. however, it may freerun with respect to all other clocks without performance degradation. d1i, d2i d channel signaling bit inputs (pins 6, 7) these i nput s a r e 1 6 k bp s s eria l d at a i nputs . t wo b its should be clocked into each of these inputs between the ris- ing edges of the msi frame reference clock. the first bit of each d channel is clocked into an intermediate buffer on the first falling edge of the dclk following the rising edge of msi. the second bit of each d channel is clocked in on the next negative t ransitio n o f t he d clk . i f f urthe r d cl k n egative edges occur , new information is serially clocked into the buf f- er r eplacin g t h e p reviou s d at a o n e b i t a t a t ime . b uffered d channel data bits are burst to the slave device on the next rising edge of the msi frame reference clock. d1o, d2o d channel signal outputs (pins 9, 10) these serial outputs provide the 16 kbps d channel signal - ing information from the incoming burst. t wo data bits should be clocked out of each of these outputs between the rising edges of the msi frame reference clock. the rising edge of msi produces the first bit of each d channel on its respective pin. circuitry then searches for a negative d channel clock edge. this tells the d channel data shift register to produce the s econ d d c hanne l b i t o n t h e n ex t r isin g e dg e o f t he dclk. further positive edges of the dclk recirculate the d channel output buffer information. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc145421 ? mc145425 motorola 6 dclk d channel clock input (pin 8) this input is the transmit and receive data clock for both d channels. d c hanne l i npu t a n d o utput o peratio n i s d e- scribed in the d1o, d2o pin description. tx transmit data output (pin 13) this pin is high impedance when both te1 and te2 are low. this pin serves as an output for b channel information received from the slave device. the b channel data is under the c ontro l o f t e1 , t e2 , a n d t dc/rdc . ( se e t e1 , t e2 description.) rx receive data input (pin 21) b channel data is input on this pin and is controlled by the re1, re2, and tdc/rdc pins. (see re1, re2 description.) te1, te2 transmit data enable input (pins 14, 15) these two pins control the output of data for their respec - tive b channel on the tx output pin. when both te1 and te2 are low , the tx pin is high impedance. the rising edge of the respective e nable p roduce s t h e f irs t b i t o f t h e s elected b channel data on the tx pin. internal circuitry then scans for the next negative transition of the tdc/rdc clock. following this event, the next seven bits of the selected b channel data are output on the next seven rising edges of the tdc/rdc data clock. when te1 and te2 are high simultaneously , data on the tx pin is undefined. te1 and te2 should be approxi - mately leadingedge aligned with the tdc/rdc data clock signal. in order to keep the tx pin out of the highimpedance state, these enable lines should be high while the respective b channel data is being output. re1, re2 receive data enable inputs (pins 19, 20) these inputs control the input of b channel data on the rx pin of the device. the rising edge of the respective enable signal causes the device to load the selected receive data buffer w it h d at a f ro m t h e r x p i n o n t h e n ex t e igh t f alling edges o f t he t dc/rd c c loc k i nput . t h e r e 1 a n d r e2 enable s s hould b e r oughl y l eadingedg e a ligne d w it h t he tdc/rdc data clock input. these enables are rising edge sensitive and need not be high for the entire b channel input period. tdc/rdc transmit/receive data clock input (pin 18) this input is the transmit and receive data clock for the b channel data. as described in the te1/te2 and the re1/ re2 sections, output data changes state on the rising edge of this signal, and input data is read on the falling edges of this s ignal . t dc/rd c s houl d b e r oughl y l eadingedge aligned with the te1, te2, re1, and re2 enables, as well as the msi frame reference signal. mc145425 slave pin descriptions v dd positive supply (pin 24) the most positive power supply pin, normally + 5 v with respect to v ss . v ss negative supply (pin 1) the most negative supply pin and logic ground, normally 0 v. v ref reference output (analog ground) (pin 2) this pin is the output of the internal reference supply and should be bypassed to v dd and v ss with 0.1 m f capacitors. this pin usually serves as an analog ground reference for transformer coupling of the device' s incoming bursts from the line. no external dc load should be placed on this pin. li line input (pin 3) this pin is an input to the demodulator for the incoming bursts. the input has an internal 240 k w resistor tied to the v ref pin, an external capacitor or line transformer may be used to couple the input signal to the device with no dc of fset. lo1, lo2 line driver outputs (pins 23, 22) these pushpull outputs drive the twisted pair transmis - sion line with a 512 khz modified dpsk (mdpsk) burst each 125 m s; in other words at an 8 khz frame rate. when not modulating the line, these pins are driven to the active high state e being the same potential, they create an ac short. when used in conjunction with feed resistors, proper line ter - mination is maintained. clk out clock output (pin 19) this p i n s erve s a s a b uffere d o utpu t o f t h e c rysta l f re- quency divided by two. this clock is provided for systems using the mc145428 data set interface asynchronous/syn - chronous terminal adaptor device. lb loopback control input (pin 4) when this pin is low , the incoming b channels from the master are burst back to the master e instead of the rx b channel input data. the b channel data from the master con - tinues to be output at the slave' s tx pin during loopback. if the to ne a n d t h e l oopbac k f unctio n a r e a ctiv e s imulta- neously, the loopback function overrides the tone function. d channel data is not affected by lb . vd valid data output (pin 5) a high on this pin indicates that a valid transmission burst has been demodulated. a valid burst is determined by proper synchronization and the absence of detected bit errors. if no transmissions from the master have been received in the last 250 m s, as determined by an internal oscillator , vd will go low. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc145421 ? mc145425 motorola 7 mu/a tone format input (pin 11) this pin determines the pcm code for the 500 hz square wave tone generated when the t one input is high e mu law (mu/a = 1) or ccitt alaw (mu/a = 0) format. tone tone enable input (pin 16) a high on this pin causes a 500 hz square wave pcm tone to be inserted in place of the demodulated b channel data on b c hanne l 1 . t hi s f eatur e a llow s t h e d esigne r t o p rovide audio feedback for telset keyboard operations. pd power down input/output (pin 12) this is a bidirectional pin with a weak output driver so that it c a n b e e xternall y o verdriven . w he n h el d l ow , t h e i sdn udlt is powered down, and the only active circuitry is that which i s n ecessar y f o r d emodulation , g eneratio n o f e n1, en2, bclk, and dclk, and outputting of the data bits and vd. w he n h el d h igh , t h e i sd n u dl t i s p owere d u p a nd transmits normally in response to received bursts from the master. if the isdn udlt is powered up for 250 m s e which is derived from an internal oscillator and no bursts from the master have occurred e t he i sd n s lav e u dl t g enerates a freerunnin g s et o f e n1 , en2, bclk, and dclk signals and sends a burst to the master device every other 125 m s frame. this is a wakeup signal to the master. when pd is floating and a burst from the master is demod - ulated, the weak output drivers will try to force pd high. it will try to force pd low if 250 m s have elapsed without a burst from the master being successfully demodulated. this allows the s lav e d evic e t o s el f p owe r u p a n d d ow n i n d emand powered loop systems. cci crystal input (pin 17) normally, an 8.192 mhz crystal is tied between this pin and the xtl pin. a 10 m w resistor between cci and xtl and 25 pf capacitors from cci and xtl to v ss are required to ensure stability and startup. cci may also be driven with an external 8.192 mhz signal if a crystal is not desired. xtl crystal output (pin 18) this pin is capable of driving one external cmos input and 15 pf of additional load capacitance. d1i, d2i d channel inputs (pins 6, 7) these two pins are inputs for the 16 kbps d data channels. the d channel data bits are clocked in serially on the nega - tive edge of the 16 kbps dclk output pin. d1o, d2o d channel outputs (pins 9, 10) these two pins are outputs for the 16 kbps d data chan - nels. these pins are updated on the rising edges of the slave dclk output pin. tx transmit data output (pin 13) this line is an output for the b channel data received from the master . b channel 1 data is output on the first eight cycles of the bclk output when en1 is high. b channel 2 data is output on the next eight cycles of the bclk, when en2 is high. b channel data bits are clocked out on the rising edge of the bclk output pin. dclk d channel clock output (pin 8) this output is the transmit and receive data clock for both d channels. it starts upon demodulation of a burst from the master d evice . t hi s s igna l i s r isin g e dg e a ligne d w it h t he en1 and bclk signals. after the demodulation of a burst, the dclk line completes two cycles and then remains low until another burst from the master is demodulated. in this manner synchronization with the master is established and any clock slip between master and slave is absorbed each frame. rx receive data input (pin 21) this pin is an input for the b channel data. b channel 1 data is clocked in on the first eight falling edges of the bclk output following the rising edge of the en1 output. b channel 2 data is clocked in on the next eight falling edges of the bclk following the rising edge of the en2 output. en1 b channel 1 enable output (pin 15) this line is an 8 khz enable signal for the input and output of the b channel 1 data. while en1 is high, b channel 1 data is clocked out on the tx pin on the first eight rising edges of the bclk. during this same time, b channel 1 input data is clocked in on the rx pin on the first eight falling edges of the bclk. the vd pin is also updated on the rising edge of the en1 signal. en1 serves as the slave device' s 8 khz frame reference signal. en2 b channel 2 enable output (pin 14) this pin is the logical inverse of the en1 output and is used to signal the time slot for the input and output of data for the b channel 2 data. bclk b channel data clock output (pin 20) this is a standard b series output which provides the data clock for the b channel data. this clock signal is 128 khz and begins o peratin g u po n t h e s uccessfu l d emodulatio n o f a burst from the master . at this time, en1 goes high and bclk starts toggling. bclk remains active for 16 periods, at the end of which time it remains low until another burst is re - ceived from the master . in this manner synchronization be - tween t h e m aste r a n d s lav e i s e stablishe d a n d a n y c lock slippage is absorbed each frame. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc145421 ? mc145425 motorola 8 background the mc145421 and the mc145425 isdn udl t s provide an economical means of sending and receiving two b chan - nels ( 6 4 k bp s e ach ) o f v oice/dat a a n d t w o d c hannels (16 kbps each) of signal data in a twowire configuration at distances up to one kilometer . there are two isdn udl ts, master and slave. the master udl t is compatible with exist - ing and evolving p abx architectures. this device transmits 2b+2d channels of data to the remote slave. at the remote end, the slave device presents a replica of the pbx back - plane to the terminal devices. these devices permit existing digital pbx architectures to remain unchanged and provide enhanced voice/data com - munication services throughout the pbx service area by sim - ply replacing a subscriber's line card and telset. all o peration s o ccu r w ithi n t h e b oundarie s o f a n 8 khz frame (125 m s). in the master , the frame sequence begins on the rising edge of msi. in the slave, the frame begins after the demodulation of a burst from the master . the slave initial - izes its timing controls at this point to stay synchronized with the master. during o n e 1 25 m s f ram e f ou r m ai n a ctivitie s a r e p er- formed: 1. previously buf fered 2b+2d channel data is burst to the other end. 2. new 2b+2d channel data is accepted for the next frame's transmission. 3. an incoming burst is demodulated and stored. 4. 2b+2d channel data from the previous demodulated frame is output. the bursts are 20 bits long, composed of two 8bit b chan - nels and two 2bit d channels. bursts are encoded using a modified dpsk method at 512 khz. since a single wire pair is used, halfduplex operation is used. a 512 khz burst is sent from end to end in a pingpong fashion. this method provides apparent fullduplex 160 kbps transmission of data at distances up to one kilometer. general the isdn udl t consists of a modulator , a demodulator , intermediate data registers, receive and transmit data regis - ters, and sequencing and control logic. the rx and tx buf f- ers interface digitally to the line card backplane signals, while the modulator and demodulator interface to the twisted pair transmission media. intermediate data registers buf fer data between t hes e m ai n c omponents . t h e i sd n u dl t i s i n- tended to operate with a 5 v power supply and can be driven by cmos or ttl logic. master operation in the master , the rising edge of msi initiates the 125 m s frame. b channel data is clocked into the rx registers under control of tdc/rdc, re1, and re2. this data is combined with the d channel data clocked in on pins d1i and d2i by the dclk. t h e r esultin g 2 0bi t p acke t i s s tored f o r t h e n ext frame transmission to the slave udlt. the burst output to the slave consists of the 2b+2d data loaded during the previous frame. the burst received from the slave is demodulated and stored for outputting in the fol- lowing frame. b channel bits demodulated in the previous frame are out - put on the tx pin under control of tdc/rdc, te1, and te2. demodulated d channel bits are output on the d1o and d2o output pins. the indication of a valid burst demodulation is the vd output, which is updated at the start of every frame. slave operation in normal slave operation, the main synchronizing event is completion of demodulating a burst from the master udl t. this action initializes the 125 m s frame boundary of the slave. during the slave frame, b channel data is loaded and stored under control of the bclk, en1, and en2 outputs. d channel data is loaded at d1i and d21 under control of the dclk output. the demodulated burst from the master is separated into its d channel and b channel components and output on the d1o, d2o, and tx pins. the return burst to the master con- sisting of previously loaded 2b+2d data is transmitted eight bauds after the completion of demodulation of the master 's burst. this provides a period for line transients to diminish. the s tar t o f t h e s lav e f ram e i nitiate s t w o c ycle s o f t he 16 khz dclk, and one cycle each of the 8 khz en1 and en2 enables. after completing their cycles, these outputs remain low u nti l a nothe r d emodulatio n s ignal s t h e s tar t o f a n ew slave frame. in this manner , clock slip between the master and slave udlts is absorbed each frame. powerdown operation when pd is low in the master, the isdn udlt is powered down a n d o nl y t ha t c ircuitr y n ecessar y t o d emodulat e i n- coming bursts is active. no transmissions to the slave occur during power down. if the master is receiving bursts from the slave, the vd pin will change state upon completion of the demodulation. when the pd input pin is driven high, the master isdn udlt is powered up. in this mode, the master bursts to the slave every frame. b and d channel data can be loaded and unloaded and vd is updated on the msi rising edge. if no bursts are received by the master , whether powered up or not, the b channel data is unknown and the d channel bits will remain at their last known values. the pd pin on the slave udlt is bidirectional with a weak output driver that can be overdriven externally . when low , either externally or internally derived, the slave is powered down. no bursts to the master can be transmitted. en1, en2, bclk, and dclk outputs are inactive during power down except when t one is high or a burst has been received from the master . b and d channel data can be loaded and un - loaded, and vd is updated upon completion of demodulation of an incoming burst from the master. input b and d channel data is not transmitted until the slave is powered up, in which case the first burst contains the most recently loaded data. when t h e p d p i n i s h igh , t h e s lav e i s p owere d u p a nd transmits every frame, the data enables and clocks are out - put, and data can be loaded and unloaded. timeout operation timeout is an operating state in both the udl t master and s lave d evices . t hi s s tat e i ndicate s t ha t n o i ncoming bursts have been demodulated, forcing the vd pin low . an internal counter is incremented for each frame that does not contain a n i ncomin g b urst . t h e c ounte r i s r ese t u po n d e- modulating a b urs t f ro m t h e f a r e nd . t imeou t c a n o ccur whether the device is powered up or down. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc145421 ? mc145425 motorola 9 in the master , timeout begins on the rising edge of the third msi following the last received burst. this is equivalent to two msi frames. the vd output is forced low during time out. t h e b c hanne l o utpu t d at a w il l b e u nknown , b u t t he d channel bits will remain at their last values. successful de - modulation of a burst from the slave will result in leaving the timeout state on the next rising msi edge. when the pd pin is used as an output on the slave udl t, timeout controls the pin. t imeout forces the pd output low to indicate that the device has powered itself down. in this case, t h e s lave w il l n o t t ransmi t t o t h e m aster . h owever, when a valid burst is received, timeout ends and the pd pin is driven high to indicate power up. this feature allows the slave udlt to selfpowerup and down in demandpowered loop systems. note the slave uses a free running clock during time out. after a long period without a burst from the master, t he t imin g b etwee n m aste r a n d s lave could be such that more than one burst will be needed to resync the two devices. 125 m s 1st bit 2nd bit 1st bit 2nd bit b channel 1 output b channel 2 output b channel 2 input b channel 1 input highz msi vd dclk d1i, d2i d1o, d2o tdc/rdc te1 te2 re1 re2 tx rx don't care figure 1. typical mc145421 master isdn udlt timing f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc145421 ? mc145425 motorola 10 125 m s 1st bit 1st bit 2nd bit 2nd bit b channel 1 output b channel 2 output b channel 1 input b channel 2 input slip absorbed 1 8 9 16 en1 en2 dclk vd d1i, d2i d1o, d2o tx rx bclk figure 2. mc145425 slave isdn udlt timing top trace: msi bottom t race: outgoing burst measured at li (with respect to v ref ) figure 3. master burst f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc145421 ? mc145425 motorola 11 110 w 110 w 110 w 110 w + 5 v + 5 v + 5 v 5 k w 10 k w l2 l1 twisted pair wire lo1 lo2 v ref li master or slave isdn udlt + 5 v 0.1 m f 0.1 m f rx tx inductance of tx: winding: 1.75 mh turns ratio: tx l1 + l2 2:1 turns ratio: rx l1 + l2 4:1 diodes: 1n4148 or equivalent transformer parameters figure 4. interface to twisted pair wire f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc145421 ? mc145425 motorola 12 switching characteristics (v dd = 5 v, t a = 0 to 70 c; c load = 50 pf) no.* parameter min max unit master timing 1 tdc/rdc pulse width high 110 e ns 2 tdc/rdc pulse width low 110 e ns 3 msi rising edge to tdc/rdc falling edge 90 e ns 4 msi pulse width 200 e ns 5 msi rising edge to first dclk falling edge 90 e ns 6 msi rising edge to first d1o, d2o bit valid e 100 ns 7 te1, te2 rising edge to tdc/rdc falling edge 110 e ns 8 tdc/rdc falling edge to te1, te2 rising edge 20 e ns 9 te1, te2 rising edge to first tx data bit v alid e 50 ns 10 tdc/rdc rising edge to tx data bits 2 through 8 v alid e 50 ns 11 te1, te2 falling edge to tx highimpedance e 70 ns 12 rei, re2 rising edge to tdc/rdc falling edge 110 e ns 13 tdc/rdc falling edge to re1, re2 rising edge 20 e ns 14 rx data setup (data valid before tdc/rdc falling edge) 50 e ns 15 rx data hold (data valid after tdc/rdc falling edge) 20 e ns 16 re1, re2 pulse width 220 e ns 17 dclk rising edge to d1o, d2o bit valid e 135 ns 18 d1i, d2i data setup (data valid before dclk falling edge) 50 e ns 19 d1i, d2i data hold (data valid after dclk falling edge) 20 e ns 20 dclk pulse width low 110 e ns 21 dclk pulse width high 110 e ns 22 msi rising edge to vd valid e 150 ns 23 pd , lb setup (pd , lb valid before msi rising edge) 50 e ns 24 pd , lb hold (pd , lb valid after msi rising edge) 20 e ns slave timing 25 bclk pulse width high (cci = 8.192 mhz) 3.66 4.15 m s 26 bclk pulse width low (cci = 8.192 mhz) 3.66 4.15 m s 27 en1 or en2 rising edge to bclk rising edge 75 175 ns 28 en1 or en2 rising edge to dclk rising edge e 50 ns 29 en1 or en2 rising edge to first tx data bit valid e 50 ns 30 bclk rising edge to tx data bits 2 through 8 v alid e 75 ns 31 dclk pulse width high (cci = 8.192 mhz) 31.0 31.5 m s 32 dclk pulse width low (cci = 8.192 mhz) 31.0 31.5 m s 33 dclk rising edge to d1o, d2o bits valid e 50 ns 34 rx setup (rx data v alid before bclk falling edge) 175 e ns 35 rx hold (rx data valid after bclk falling edge) 20 e ns 36 d1i, d2i setup (d1i, d2i valid before dclk falling edge) 50 e ns 37 d1i, d2i hold (d1i, d2i valid after dclk falling edge) 20 e ns 38 en1 rising edge to vd valid e 50 ns se pin timing 39 lb , pd hold (lb , pd valid after se falling edge) 20 e ns 40 d1o, d2o, vd high impedance after se falling edge e 70 ns 41 d1o, d2o, vd valid after se rising edge 60 e ns 42 lb , pd setup (lb , pd valid before se rising edge) 50 e ns * see switching characteristics waveforms. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc145421 ? mc145425 motorola 13 note: all measurement thresholds are 30% or 70% of v . dd msi tdc/rdc te1, te2 tx re1, re2 rx dclk d1o, d2o d1i, d2i vd pd, lb don't care bit 1 valid da ta bit valid don't care don't care don't care don't care don't care bit 1 bit 2 bit 2 8 7 6 5 4 3 2 1 4 3 1 2 11 7 8 9 10 12 13 14 15 5 16 17 6 21 20 18 23 24 22 19 8 7 6 5 4 3 2 1 master switching characteristics f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc145421 ? mc145425 motorola 14 slave switching characteristics master se pin timing previous st ate internally la tched valid valid se lb, pd d1o, d2o, vd 39 40 41 42 bclk en1 en2 tx rx dclk d1o, d2o d1i, d2i vd valid don't care bit 2 don't care don't care don't care bit 1 bit 1 bit 2 26 27 28 29 30 31 32 33 34 35 36 37 38 25 28 33 27 29 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 1 note: all measurement thresholds are 30% or 70% of v dd . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc145421 ? mc145425 motorola 15 package dimensions p suffix plastic package case 70902 min min max max millimeters inches dim a b c d f g h j k l m n 31.37 13.72 3.94 0.36 1.02 1.65 0.20 2.92 0 0.51 32.13 14.22 5.08 0.56 1.52 2.03 0.38 3.43 15 1.02 1.235 0.540 0.155 0.014 0.040 0.065 0.008 0.115 0 0.020 1.265 0.560 0.200 0.022 0.060 0.080 0.015 0.135 15 0.040 2.54 bsc 15.24 bsc 0.100 bsc 0.600 bsc notes: 1. positional tolerance of leads (d), shall be within 0.25 (0.010) at maximum material condition, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 1 12 13 24 b a n seating plane m j l d f g h c k dw suffix sog package case 751f04 min min max max millimeters inches dim a b c d f g j k m p r 17.80 7.40 2.35 0.35 0.41 0.23 0.13 0 10.05 0.25 18.05 7.60 2.65 0.49 0.90 0.32 0.29 8 10.55 0.75 0.701 0.292 0.093 0.014 0.016 0.009 0.005 0 0.395 0.010 0.711 0.299 0.104 0.019 0.035 0.013 0.011 8 0.415 0.029 1.27 bsc 0.050 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. -a- -b- 1 14 15 28 -t- c seating plane 0.010 (0.25) b m m m j -t- k 26x g 28x d 14x p r x 45 f 0.010 (0.25) t a b m s s f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .
mc145421 ? mc145425 motorola 16 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer . how to reach us: usa/europe : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, toshikatsu otsuki, p.o. box 20912; phoenix, arizona 85036. 18004412447 6f seibubutsuryucenter, 3142 tatsumi kotoku, tokyo 135, japan. 0335218315 h o n g k o n g : m o t o r o l a s e m i c ondu c t o r s h . k . l t d . ; 8 b t a i p i n g i ndu s t r i a l p a r k , i 5 1 t i n g k o k r oad , t a i p o , n . t . , h on g k ong . 8 522662929 8 mc145421/d ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . a r c h i v e d b y f r e e s c a l e s e m i c o n d u c t o r , i n c .

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